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Home » MCQs » VHDL MCQs

VHDL | Variables are assigned using which of the following?

57. Variables are assigned using which of the following?

  1. ::<
  2. =<
  3. <=
  4. :<

Answer: D) :<

Explanation:

Variables are assigned using variable assignment statements (:<) and are immediately updated inside the scope of the current scope.

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